415 search results - page 18 / 83 » Comparative evaluation of memory models for chip multiproces... |
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
As transistor density continues to grow at an exponential rate in accordance to Moore’s law, the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-ch...
ASPLOS
2006
ACM
13 years 11 months ago
2006
ACM
Architects use cycle-by-cycle simulation to evaluate design choices and understand tradeoffs and interactions among design parameters. Efficiently exploring exponential-size desig...
ISPASS
2005
IEEE
14 years 1 months ago
2005
IEEE
We introduce a fast and accurate technique for initializing the directory and cache state of a multiprocessor system based on a novel software structure called the memory timestam...
PPOPP
2009
ACM
14 years 8 months ago
2009
ACM
On multiprocessors with explicitly managed memory hierarchies (EMM), software has the responsibility of moving data in and out of fast local memories. This task can be complex and...