415 search results - page 27 / 83 » Comparative evaluation of memory models for chip multiproces... |
ISCA
2000
IEEE
14 years 2 days ago
2000
IEEE
Spatial-lattice computations with finite-range interactions are an important class of easily parallelized computations. This class includes many simple and direct algorithms for ...
HPCA
2007
IEEE
14 years 8 months ago
2007
IEEE
This paper evaluates the suitability of the MapReduce model for multi-core and multi-processor systems. MapReduce was created by Google for application development on data-centers...
ISCA
2008
IEEE
14 years 2 months ago
2008
IEEE
Efficiently utilizing off-chip DRAM bandwidth is a critical issue in designing cost-effective, high-performance chip multiprocessors (CMPs). Conventional memory controllers deli...
ATS
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract: Fabrication process improvements and technology scaling results in modifications in the characteristics and in the behavior of manufactured memory chips, which also modi...
GLVLSI
2000
IEEE
14 years 3 days ago
2000
IEEE
— Typically, placement algorithms attempt to minimize the total net length of a printed circuit board (PCB). However, an MCM’s increased throughput and dense circuitry can easi...