Sciweavers

415 search results - page 36 / 83
» Comparative evaluation of memory models for chip multiproces...
Sort
View
WMPI
2004
ACM
14 years 1 months ago
SCIMA-SMP: on-chip memory processor architecture for SMP
Abstract. In this paper, we propose a processor architecture with programmable on-chip memory for a high-performance SMP (symmetric multi-processor) node named SCIMA-SMP (Software ...
Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, ...
ITC
2000
IEEE
76views Hardware» more  ITC 2000»
14 years 1 days ago
Industrial evaluation of DRAM SIMM tests
This paper describes the results of testing 50 single inline memory modules (SIMMs), each containing 16 16Mbit DRAM chips (DUTs); 39 SIMMs failed, and of the 800 DUTs, 116failed. ...
A. J. van de Goor, A. Paalvast
WSC
1997
13 years 9 months ago
Modeling a 10 Gbit/s/Port Shared Memory ATM Switch
The speed of optical transmission links is growing at a rate which is difficult for the micro-electronic technology of ATM switches to follow. In order to cover the transmission r...
Tawfik Lazraq, Jakob Brundin, Per Andersson, &Arin...
CAV
2004
Springer
151views Hardware» more  CAV 2004»
13 years 11 months ago
QB or Not QB: An Efficient Execution Verification Tool for Memory Orderings
We study the problem of formally verifying shared memory multiprocessor executions against memory consistency models--an important step during post-silicon verification of multipro...
Ganesh Gopalakrishnan, Yue Yang, Hemanthkumar Siva...
ISCA
2007
IEEE
162views Hardware» more  ISCA 2007»
14 years 2 months ago
BulkSC: bulk enforcement of sequential consistency
While Sequential Consistency (SC) is the most intuitive memory consistency model and the one most programmers likely assume, current multiprocessors do not support it. Instead, th...
Luis Ceze, James Tuck, Pablo Montesinos, Josep Tor...