415 search results - page 38 / 83 » Comparative evaluation of memory models for chip multiproces... |
176
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IPPS
2006
IEEE
16 years 3 hour ago
2006
IEEE
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
186
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ICPP
2009
IEEE
16 years 19 days ago
2009
IEEE
—Lattice Boltzmann Methods (LBM) are used for the computational simulation of Newtonian fluid dynamics. LBM-based simulations are readily parallelizable; they have been implemen...
181
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IEEEPACT
2006
IEEE
16 years 8 hour ago
2006
IEEE
As chip multiprocessors (CMPs) become increasingly mainstream, architects have likewise become more interested in how best to share a cache hierarchy among multiple simultaneous t...
166
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ISCA
2011
IEEE
14 years 9 months ago
2011
IEEE
Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the enti...
143
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ISCA
2000
IEEE
15 years 10 months ago
2000
IEEE
This paper evaluates performance characteristics of the Compaq ES40 shared memory multiprocessor. The ES40 system contains up to four Alpha 21264 CPU’s together with a high-perf...