Sciweavers

415 search results - page 45 / 83
» Comparative evaluation of memory models for chip multiproces...
Sort
View
ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
13 years 12 months ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
ISCA
1997
IEEE
108views Hardware» more  ISCA 1997»
13 years 12 months ago
The SGI Origin: A ccNUMA Highly Scalable Server
The SGI Origin 2000 is a cache-coherent non-uniform memory access (ccNUMA) multiprocessor designed and manufactured by Silicon Graphics, Inc. The Origin system was designed from t...
James Laudon, Daniel Lenoski
IEEEHPCS
2010
13 years 6 months ago
Analytical modeling and evaluation of network-on-chip architectures
Network-on-chip (NoC) architectures adopted for Systemon-Chip (SoC) are characterized by different trade-offs between latency, throughput, communication load, energy consumption, ...
Suboh A. Suboh, Mohamed Bakhouya, Jaafar Gaber, Ta...
TCAD
2010
124views more  TCAD 2010»
13 years 2 months ago
A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms
Abstract--This paper presents a GALS-compatible circuitswitched on-chip network that is well suited for use in many-core platforms targeting streaming DSP and embedded applications...
Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas
DATE
2004
IEEE
129views Hardware» more  DATE 2004»
13 years 11 months ago
Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach
Future Systems-on-Chips will include multiple heterogeneous processing units, with complex data-dependent shared resource access patterns dictating the performance of a design. Cu...
Alex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, ...