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» Comparing designs for computer simulation experiments
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DCC
2008
IEEE
13 years 10 months ago
Design and Implementation of a High-Performance Microprocessor Cache Compression Algorithm
Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functional...
Xi Chen, Lei Yang, Haris Lekatsas, Robert P. Dick,...
PG
2007
IEEE
14 years 3 months ago
Illumination Brush: Interactive Design of All-Frequency Lighting
We present an appearance-based user interface for artists to efficiently design customized image-based lighting environments. 1 Our approach avoids typical iterations of paramete...
Makoto Okabe, Yasuyuki Matsushita, Li Shen, Takeo ...
ICCAD
2008
IEEE
125views Hardware» more  ICCAD 2008»
14 years 5 months ago
A succinct memory model for automated design debugging
— In today’s complex SoC designs, verification and debugging are becoming ever more crucial and increasingly timeconsuming tasks. The prevalence of embedded memories adds to t...
Brian Keng, Hratch Mangassarian, Andreas G. Veneri...
GLVLSI
2009
IEEE
125views VLSI» more  GLVLSI 2009»
14 years 21 days ago
Spatial and temporal design debug using partial MaxSAT
Design debug remains one of the major bottlenecks in the VLSI design cycle today. Existing automated solutions strive to aid engineers in reducing the debug effort by identifying ...
Yibin Chen, Sean Safarpour, Andreas G. Veneris, Jo...
DAC
2005
ACM
13 years 10 months ago
Performance space modeling for hierarchical synthesis of analog integrated circuits
Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient ...
Georges G. E. Gielen, Trent McConaghy, Tom Eeckela...