622 search results - page 12 / 125 » Comparing the Optimal Performance of Multiprocessor Architec... |
IPPS
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents reduction recognition and parallel code generationstrategies for distributed-memorymultiprocessors. We describe techniques to recognize a broad range of implic...
SBACPAD
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
Commercial applications are an important, yet often overlooked, workload with significantly different characteristics from technical workloads. The potential impact of these diffe...
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
CODES
2003
IEEE
14 years 20 days ago
2003
IEEE
In the Sesame framework, we develop a modeling and simulation environment for the efficient design space exploration of heterogeneous embedded systems. Since Sesame recognizes se...