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» Comparing the Optimal Performance of Parallel Architectures
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Publication
767views
15 years 6 months ago
Analysis of the Increase/Decrease Algorithms for Congestion Avoidance in Computer Networks
Congestion avoidance mechanisms allow a network to operate in the optimal region of low delay and high throughput, thereby, preventing the network from becoming congested. This is ...
D. Chiu and R. Jain
DAC
2003
ACM
14 years 9 months ago
Distributed sleep transistor network for power reduction
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
Changbo Long, Lei He
DAC
2006
ACM
14 years 9 months ago
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inve...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...
VLSID
2008
IEEE
111views VLSI» more  VLSID 2008»
14 years 8 months ago
Power Reduction of Functional Units Considering Temperature and Process Variations
Continuous technology scaling has resulted in an increase in both, the power density as well as the variation in device dimensions (process variations) of the manufactured process...
Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj...
VLSID
2002
IEEE
122views VLSI» more  VLSID 2002»
14 years 8 months ago
Evaluating Run-Time Techniques for Leakage Power Reduction
While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimization...
David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishn...