1461 search results - page 8 / 293 » Comparing the Optimal Performance of Parallel Architectures |
IPPS
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper presents an extensive characterization, tuning, and optimization of parallel I/O on the Cray XT supercomputer, named Jaguar, at Oak Ridge National Laboratory. We have c...
IPPS
1997
IEEE
13 years 11 months ago
1997
IEEE
An analysis is presented of the primary factors influencing the performance of a parallel implementation of the UCLA atmospheric general circulation model (AGCM) on distributedme...
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...
ISCAS
2002
IEEE
14 years 8 days ago
2002
IEEE
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
CSE
2009
IEEE
13 years 10 months ago
2009
IEEE
Sparse Matrix-Vector multiplication (SpMV) is a very challenging computational kernel, since its performance depends greatly on both the input matrix and the underlying architectur...