59 search results - page 6 / 12 » Comparing the latency performance of the DTable and DRR sche... |
ISCA
2008
IEEE
14 years 2 months ago
2008
IEEE
In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by cau...
JUCS
2000
13 years 8 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
HEURISTICS
2008
13 years 8 months ago
2008
Instruction scheduling is an important step for improving the performance of object code produced by a compiler. A fundamental problem that arises in instruction scheduling is to ...
MASCOTS
2003
13 years 10 months ago
2003
Access latency to secondary storage devices is frequently a limiting factor in computer system performance. New storage technologies promise to provide greater storage densities a...
ICCD
2006
IEEE
14 years 5 months ago
2006
IEEE
This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction sc...