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» Compiled-code-based simulation with timing verification
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CONCUR
2010
Springer
13 years 7 months ago
Conditional Automata: A Tool for Safe Removal of Negligible Events
Abstract. Polynomially accurate simulations [19] are relations for Probabilistic Automata that require transitions to be matched up to negligible sets provided that computation len...
Roberto Segala, Andrea Turrini
TVLSI
2002
130views more  TVLSI 2002»
13 years 7 months ago
Incremental compilation for parallel logic verification systems
Although simulation remains an important part of application-specific integrated circuit (ASIC) validation, hardware-assisted parallel verification is becoming a larger part of the...
R. Tessier, S. Jana
EURODAC
1995
IEEE
156views VHDL» more  EURODAC 1995»
13 years 11 months ago
VHDL quality: synthesizability, complexity and efficiency evaluation
With VHDL models increasing their size, it becomes more important to assure the quality of these descriptions in order to improve simulation performances, to make project maintain...
M. Mastretti
CASE
2011
102views more  CASE 2011»
12 years 7 months ago
Towards an automated verification process for industrial safety applications
— Legacy systems that do not conform to the norms and regulations imposed by recent safety standards have to be upgraded to meet safety requirements. In this paper, we describe a...
Kleanthis Thramboulidis, Doaa Soliman, Georg Frey
CODES
2003
IEEE
14 years 25 days ago
Virtual synchronization technique with OS modeling for fast and time-accurate cosimulation
Hardware/Software cosimulation is the key process to shorten the design turn around time. We have proposed a novel technique, called virtual synchronization, for fast and time acc...
Youngmin Yi, Dohyung Kim, Soonhoi Ha