118 search results - page 10 / 24 » Compiler Support for Exploiting Coarse-Grained Pipelined Par... |
132
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IEEEPACT
2002
IEEE
15 years 8 months ago
2002
IEEE
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...
239
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ASPLOS
2009
ACM
16 years 4 months ago
2009
ACM
Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity processors in high-performance text processing applications such as UTF8 to UTF-...
166
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SP
2008
IEEE
15 years 3 months ago
2008
IEEE
We have developed an environment, based upon robust, existing, open source software, for tuning applications written using MPI, OpenMP or both. The goal of this effort, which inte...
126
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ICPPW
2005
IEEE
15 years 9 months ago
2005
IEEE
Thread-level speculation is a technique that brings thread-level parallelism beyond the data-flow limit by executing a piece of code ahead of time speculatively before all its inp...
115
Voted
ICCAD
2001
IEEE
16 years 8 days ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...