25 search results - page 4 / 5 » Compiler Supports and Optimizations for PAC VLIW DSP Process... |
LCTRTS
2005
Springer
14 years 28 days ago
2005
Springer
Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in highperformance embedded applications such as digital sign...
VLSID
1999
IEEE
13 years 11 months ago
1999
IEEE
Abstract Code optimization for digital signal processors DSPs has been identi ed as an important new topic in system-level design of embedded systems. Both DSP processors and algor...
CASES
2007
ACM
13 years 11 months ago
2007
ACM
In this paper we describe the design and implementation of a flexible, and extensible, just-in-time ARM simulator designed to run co-operatively with a multi-core DSP simulator on...
CC
2007
Springer
14 years 1 months ago
2007
Springer
To achieve high resource utilization for multi-issue Digital Signal Processors (DSPs), production compilers commonly include variants of the iterative modulo scheduling algorithm. ...
ISSS
1995
IEEE
13 years 11 months ago
1995
IEEE
The increasing usage of Application Specific Instruction Set Processors (ASIPs) in audio and video telecommunications has made strong demands on the rapid availability of dedicat...