1008 search results - page 16 / 202 » Compiler Technology for Two Novel Computer Architectures |
DAC
2005
ACM
14 years 9 months ago
2005
ACM
This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the conf...
DAC
2001
ACM
14 years 9 months ago
2001
ACM
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
RTSS
2006
IEEE
14 years 2 months ago
2006
IEEE
Real-time systems design involves many important choices, including that of the processor. The fastest processors achieve performance by utilizing architectural features that make...
ECSQARU
1997
Springer
14 years 18 days ago
1997
Springer
Given a number of Dempster-Shafer belief functions there are different architectures which allow to do a compilation of the given knowledge. These architectures are the Shenoy-Sha...
DAC
2010
ACM
14 years 11 days ago
2010
ACM
Complex embedded systems have always been heterogeneous multicore systems. Because of the tight constraints on power, performance and cost, this situation is not likely to change a...