Sciweavers

1008 search results - page 19 / 202
» Compiler Technology for Two Novel Computer Architectures
Sort
View
MICRO
2003
IEEE
147views Hardware» more  MICRO 2003»
14 years 1 months ago
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...
Enric Gibert, F. Jesús Sánchez, Anto...
IAJIT
2010
107views more  IAJIT 2010»
13 years 7 months ago
Low Latency, High Throughput, and Less Complex VLSI Architecture for 2D-DFT
: This paper proposes a pipelined, systolic architecture for two- dimensional discrete Fourier transform computation which is highly concurrent. The architecture consists of two, o...
Sohil Shah, Preethi Venkatesan, Deepa Sundar, Muni...
IFIP
1998
Springer
14 years 20 days ago
Combining Static Partitioning with Dynamic Distribution of Threads
This paper presents a hybrid approach to automatic parallelization of computer programs which combines static extraction of threads (tasks) with dynamic scheduling for parallel an...
Ronald Moore, Melanie Klang, Bernd Klauer, Klaus W...
RTAS
2003
IEEE
14 years 1 months ago
Collaborative Operating System and Compiler Power Management for Real-Time Applications
Managing energy consumption has become vitally important to battery operated portable and embedded systems. A dynamic voltage scaling (DVS) technique reduces the processor’s dyn...
Nevine AbouGhazaleh, Daniel Mossé, Bruce R....
IEICET
2010
123views more  IEICET 2010»
13 years 5 months ago
TOA UWB Positioning with Two Receivers Using Known Indoor Features
Ultra-Wideband is an attractive technology for short range positioning, especially indoors. However, for normal Time of Arrival (ToA) positioning, at least three receivers with unb...
Jan Kietlinski-Zaleski, Takaya Yamazato, Masaaki K...