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CONCURRENCY
2006
140views more  CONCURRENCY 2006»
15 years 3 months ago
An efficient memory operations optimization technique for vector loops on Itanium 2 processors
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
William Jalby, Christophe Lemuet, Sid Ahmed Ali To...
159
Voted
JAIR
2010
130views more  JAIR 2010»
14 years 10 months ago
Interactive Cost Configuration Over Decision Diagrams
In many AI domains such as product configuration, a user should interactively specify a solution that must satisfy a set of constraints. In such scenarios, offline compilation of ...
Henrik Reif Andersen, Tarik Hadzic, David Pisinger
EMSOFT
2006
Springer
15 years 7 months ago
Compiler-assisted leakage energy optimization for clustered VLIW architectures
Miniaturization of devices and the ensuing decrease in the threshold voltage has led to a substantial increase in the leakage component of the total processor energy consumption. ...
Rahul Nagpal, Y. N. Srikant
ICCD
2002
IEEE
93views Hardware» more  ICCD 2002»
16 years 20 days ago
Speculative Trace Scheduling in VLIW Processors
VLIW processors are statically scheduled processors and their performance depends on the quality of the compiler’s scheduler. We propose a scheduling scheme where the applicatio...
Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhov...
IEEEPACT
2000
IEEE
15 years 8 months ago
Fine Grained Multithreading with Process Calculi
ÐThis paper presents a multithreaded abstract machine for the TyCO process calculus. We argue that process calculi provide a powerful framework to reason about fine-grained parall...
Luís M. B. Lopes, Fernando M. A. Silva, Vas...