To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
William Jalby, Christophe Lemuet, Sid Ahmed Ali To...
In many AI domains such as product configuration, a user should interactively specify a solution that must satisfy a set of constraints. In such scenarios, offline compilation of ...
Henrik Reif Andersen, Tarik Hadzic, David Pisinger
Miniaturization of devices and the ensuing decrease in the threshold voltage has led to a substantial increase in the leakage component of the total processor energy consumption. ...
VLIW processors are statically scheduled processors and their performance depends on the quality of the compiler’s scheduler. We propose a scheduling scheme where the applicatio...
Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhov...
ÐThis paper presents a multithreaded abstract machine for the TyCO process calculus. We argue that process calculi provide a powerful framework to reason about fine-grained parall...