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FPL
2008
Springer
129views Hardware» more  FPL 2008»
13 years 9 months ago
Power reduction techniques for Dynamically Reconfigurable Processor Arrays
The power consumption of Dynamically Reconfigurable Processing Array (DRPA) is quantitatively analyzed by using a real chip layout and applications taking into account the reconfi...
Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito,...
ASPDAC
2000
ACM
131views Hardware» more  ASPDAC 2000»
13 years 11 months ago
Reconfigurable synchronized dataflow processor
- This paper describes the design and implementation of a reconfigurable synchronized dataflow processor (RSDP). The RSDP can configure its hardware to directly represent dataflow ...
Hiroshi Sasaki, Hitoshi Maruyama, Hideaki Tsukioka...
RSP
2006
IEEE
116views Control Systems» more  RSP 2006»
14 years 1 months ago
Performance Evaluation of an Adaptive FPGA for Network Applications
This paper presents the design and the performance evaluation of a coarse-grain dynamically reconfigurable platform for network applications. The platform consists of two MicroBla...
Christoforos Kachris, Stamatis Vassiliadis
DATE
2005
IEEE
125views Hardware» more  DATE 2005»
14 years 1 months ago
Lightweight Multitasking Support for Embedded Systems using the Phantom Serializing Compiler
Embedded software continues to play an ever increasing role in the design of complex embedded applications. In part, the elevel of abstraction provided by a high-level programming...
André C. Nácul, Tony Givargis
ICIP
1998
IEEE
14 years 9 months ago
Hardware Architecture for Optical Flow Estimation in Real Time
Optical flow estimation from image sequences has been for several years a mathematical process carried out by general purpose processors in no real time. In this work a specific a...
Aitzol Zuloaga, José Luis Martín, Jo...