Sciweavers

559 search results - page 60 / 112
» Compiling Image Processing Applications to Reconfigurable Ha...
Sort
View
FPGA
2003
ACM
116views FPGA» more  FPGA 2003»
14 years 29 days ago
Hardware-assisted simulated annealing with application for fast FPGA placement
To truly exploit FPGAs for rapid turn-around development and prototyping, placement times must be reduced to seconds; latebound, reconfigurable computing applications may demand p...
Michael G. Wrighton, André DeHon
FCCM
2006
IEEE
120views VLSI» more  FCCM 2006»
14 years 1 months ago
FPGAs, GPUs and the PS2 - A Single Programming Methodology
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony’s Playstation 2 vector units offer scope for hardware acceleration of applications. Implementin...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...
ICIP
2004
IEEE
14 years 9 months ago
An implemented architecture of deblocking filter for H.264/AVC
H.264/AVC is a new international standard for the compression of natural video images, in which a deblocking filter has been adopted to remove blocking artifacts. In this paper, w...
Bin Sheng, Wen Gao, Di Wu
ASPDAC
2008
ACM
92views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Design space exploration for a coarse grain accelerator
- In the design process of a reconfigurable accelerator employing in an embedded system, multitude parameters may result in remarkable complexity and a large design space. Design s...
Farhad Mehdipour, Hamid Noori, Morteza Saheb Zaman...
TVLSI
2008
121views more  TVLSI 2008»
13 years 7 months ago
Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores
Recently, it has become possible to implement floating-point cores on field-programmable gate arrays (FPGAs) to provide acceleration for the myriad applications that require high-p...
Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna