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ISCAS
2006
IEEE
105views Hardware» more  ISCAS 2006»
14 years 3 months ago
A CMOS contact imager for locating individual cells
— We describe the design of a contact imager for applications in lab-on-a-chip systems, such as sample preparation and manipulation and monitoring of cells. This is a challenging...
Honghao Ji, David Sander, A. Haas, Pamela Abshire
ISCAPDCS
2007
13 years 10 months ago
Architectural requirements of parallel computational biology applications with explicit instruction level parallelism
—The tremendous growth in the information culture, efficient digital searches are needed to extract and identify information from huge data. The notion that evolution in silicon ...
Naeem Zafar Azeemi
ICPR
2004
IEEE
14 years 10 months ago
Using Multiple Graphics Cards as a General Purpose Parallel Computer : Applications to Computer Vision
Pattern recognition and computer vision tasks are computationally intensive, repetitive, and often exceed the capabilities of the CPU, leaving little time for higher level tasks. ...
James Fung, Steve Mann
FCCM
1998
IEEE
169views VLSI» more  FCCM 1998»
14 years 1 months ago
Scalable Network Based FPGA Accelerators for an Automatic Target Recognition Application
Abstract Image processing, specifically Automatic Target Recognition (ATR) in Synthetic Aperture Radar (SAR) imagery, is an application area that can require tremendous processing ...
Ruth Sivilotti, Young Cho, Wen-King Su, Danny Cohe...
ISSS
2002
IEEE
141views Hardware» more  ISSS 2002»
14 years 1 months ago
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin