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121
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ASAP
2007
IEEE
112views Hardware» more  ASAP 2007»
15 years 5 months ago
Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
Alain Darte, C. Quinson
124
Voted
WSC
1998
15 years 4 months ago
MODSIM III - a Tutorial with Advances in Database Access and HLA Support
MODSIM II is an object-oriented discrete event simulation language featuring extensive run-time libraries, graphical user interface and results presentation tools, database access...
John Goble, Brian Wood
CORR
2011
Springer
179views Education» more  CORR 2011»
14 years 10 months ago
An overview of Ciao and its design philosophy
We provide an overall description of the Ciao multiparadigm programming system emphasizing some of the novel aspects and motivations behind its design and implementation. An impor...
Manuel V. Hermenegildo, Francisco Bueno, Manuel Ca...
133
Voted
DAC
1997
ACM
15 years 7 months ago
More Practical Bounded-Skew Clock Routing
: Academic clock routing research results has often had limited impact on industry practice, since such practical considerations as hierarchical buffering, rise-time and overshoot ...
Andrew B. Kahng, Chung-Wen Albert Tsao
ECCV
2004
Springer
16 years 5 months ago
A Biologically Motivated and Computationally Tractable Model of Low and Mid-Level Vision Tasks
This paper presents a biologically motivated model for low and mid-level vision tasks and its interpretation in computer vision terms. Initially we briefly present the biologically...
Iasonas Kokkinos, Rachid Deriche, Petros Maragos, ...