1198 search results - page 77 / 240 » Compiling for EDGE Architectures |
ISCA
2000
IEEE
14 years 1 months ago
2000
IEEE
Reconfigurable hardware has the potential for significant performance improvements by providing support for applicationāspecific operations. We report our experience with Chimae...
DAC
2009
ACM
14 years 10 months ago
2009
ACM
Current compilers lack precise timing models guiding their built-in optimizations. Hence, compilers apply ad-hoc heuristics during optimization to improve code quality. One of the...
DAC
2002
ACM
14 years 10 months ago
2002
ACM
One of the primary challenges in embedded system design is designing the memory hierarchy and restructuring the application to take advantage of it. This task is particularly impo...
VLSID
2007
IEEE
14 years 9 months ago
2007
IEEE
We present AHIR, an intermediate representation (IR), that acts as a transition layer between software compilation and hardware synthesis. Such a transition layer is intended to t...
IEEEPACT
2006
IEEE
14 years 3 months ago
2006
IEEE
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...