Sciweavers

1133 search results - page 146 / 227
» Compiling for Speculative Architectures
Sort
View
IPPS
1998
IEEE
15 years 8 months ago
A Generalized Framework for Global Communication Optimization
In distributed-memory message-passing architectures reducing communication cost is extremely important. In this paper, we present a technique to optimize communication globally. O...
Mahmut T. Kandemir, Prithviraj Banerjee, Alok N. C...
DAC
1997
ACM
15 years 8 months ago
Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign
An experimental set of tools that generate instruction set simulators, assemblers, and disassemblers from a single description was developed to test if retargetable development to...
Mark R. Hartoog, James A. Rowson, Prakash D. Reddy...
138
Voted
DAC
1994
ACM
15 years 8 months ago
Synthesis of Instruction Sets for Pipelined Microprocessors
We present a systematic approach to synthesize an instruction set such that the given application software can be efficiently mapped to a parameterized, pipelined microarchitectur...
Ing-Jer Huang, Alvin M. Despain
DAC
1992
ACM
15 years 8 months ago
Synthesis from Production-Based Specifications
This paper describes a model for, and an implementation of, production-based synthesis of hardware description language (HDL) code in which the overall structure of the resultant ...
Andrew Seawright, Forrest Brewer
DATE
2004
IEEE
114views Hardware» more  DATE 2004»
15 years 7 months ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu