Sciweavers

1133 search results - page 16 / 227
» Compiling for Speculative Architectures
Sort
View
ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
13 years 12 months ago
Instruction Cache Fetch Policies for Speculative Execution
Current trends in processor design are pointing to deeper and wider pipelines and superscalar architectures. The efficient use of these resources requires speculative execution, ...
Dennis Lee, Jean-Loup Baer, Brad Calder, Dirk Grun...
ICS
2005
Tsinghua U.
14 years 1 months ago
Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation
Chip Multiprocessors (CMPs) are flexible, high-frequency platforms on which to support Thread-Level Speculation (TLS). However, for TLS to deliver on its promise, CMPs must explo...
Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin ...
CGO
2003
IEEE
14 years 1 days ago
Optimal and Efficient Speculation-Based Partial Redundancy Elimination
Existing profile-guided partial redundancy elimination (PRE) methods use speculation to enable the removal of partial redundancies along more frequently executed paths at the expe...
Qiong Cai, Jingling Xue
ICCD
2002
IEEE
93views Hardware» more  ICCD 2002»
14 years 5 months ago
Speculative Trace Scheduling in VLIW Processors
VLIW processors are statically scheduled processors and their performance depends on the quality of the compiler’s scheduler. We propose a scheduling scheme where the applicatio...
Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhov...