1133 search results - page 60 / 227 » Compiling for Speculative Architectures |
FPL
2007
Springer
14 years 2 months ago
2007
Springer
We introduce a new execution model for orchestrating the interaction between the conventional processor and the reconfigurable compute unit in adaptive computer systems. We then ...
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded...
CASES
2006
ACM
14 years 2 months ago
2006
ACM
Developing an optimizing compiler for a newly proposed architecture is extremely difficult when there is only a simulator of the machine available. Designing such a compiler requ...
ICFP
2008
ACM
14 years 8 months ago
2008
ACM
The trend in microprocessor design toward multicore and manycore processors means that future performance gains in software will largely come from harnessing parallelism. To reali...