Sciweavers

1133 search results - page 85 / 227
» Compiling for Speculative Architectures
Sort
View
VEE
2010
ACM
218views Virtualization» more  VEE 2010»
15 years 11 months ago
Improving compiler-runtime separation with XIR
Intense research on virtual machines has highlighted the need for flexible software architectures that allow quick evaluation of new design and implementation techniques. The inte...
Ben Titzer, Thomas Würthinger, Doug Simon, Ma...
MICRO
2006
IEEE
132views Hardware» more  MICRO 2006»
15 years 10 months ago
Data-Dependency Graph Transformations for Superblock Scheduling
The superblock is a scheduling region which exposes instruction level parallelism beyond the basic block through speculative execution of instructions. In general, scheduling supe...
Mark Heffernan, Kent D. Wilken, Ghassan Shobaki
MICRO
1999
IEEE
110views Hardware» more  MICRO 1999»
15 years 8 months ago
Balance Scheduling: Weighting Branch Tradeoffs in Superblocks
Since there is generally insufficient instruction level parallelism within a single basic block, higher performance is achieved by speculatively scheduling operations in superbloc...
Alexandre E. Eichenberger, Waleed Meleis
AIPS
2007
15 years 6 months ago
Evaluating Temporal Planning Domains
The last eight years have seen dramatic progress in temporal planning as highlighted by the temporal track in the last three International Planning Competitions (IPC). However, ou...
William Cushing, Daniel S. Weld, Subbarao Kambhamp...
CODES
2011
IEEE
14 years 3 months ago
SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs
Two overriding concerns in the development of embedded MPSoCs are ease of programming and hardware complexity. In this paper we present SoC-TM, an integrated HW/SW solution for tr...
Cesare Ferri, Andrea Marongiu, Benjamin Lipton, R....