Sciweavers

1133 search results - page 8 / 227
» Compiling for Speculative Architectures
Sort
View
IJPP
2000
94views more  IJPP 2000»
13 years 7 months ago
Path Analysis and Renaming for Predicated Instruction Scheduling
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
Lori Carter, Beth Simon, Brad Calder, Larry Carter...
IEEEPACT
2009
IEEE
14 years 2 months ago
Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading
— This research demonstrates that coming support for hardware transactional memory can be leveraged to significantly reduce the cost of implementing true speculative multithread...
Leo Porter, Bumyong Choi, Dean M. Tullsen
MICRO
1999
IEEE
131views Hardware» more  MICRO 1999»
13 years 11 months ago
Value Prediction for Speculative Multithreaded Architectures
The speculative multithreading paradigm (speculative threadlevel parallelism) is based on the concurrent execution of control-speculative threads. The efficiency of microarchitect...
Pedro Marcuello, Jordi Tubella, Antonio Gonz&aacut...
HPCA
1998
IEEE
13 years 11 months ago
Speculative Versioning Cache
Dependences among loads and stores whose addresses are unknown hinder the extraction of instruction level parallelism during the execution of a sequential program. Such ambiguous ...
Sridhar Gopal, T. N. Vijaykumar, James E. Smith, G...
IEEEINTERACT
2003
IEEE
14 years 18 days ago
Compiler Support for Dynamic Speculative Pre-Execution
Speculative pre-execution is a promising prefetching technique which uses an auxiliary assisting thread in addition to the main program flow. A prefetching thread (p-thread), whic...
Won Woo Ro, Jean-Luc Gaudiot