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» Compiling for Speculative Architectures
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SAC
2006
ACM
15 years 10 months ago
A concurrent reactive Esterel processor based on multi-threading
Esterel is a concurrent synchronous language for developing reactive systems. As an alternative to the classical software and hardware synthesis paths, the reactive processing app...
Xin Li, Reinhard von Hanxleden
ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
15 years 8 months ago
Performance Comparison of ILP Machines with Cycle Time Evaluation
Many studies have investigated performance improvement through exploiting instruction-level parallelism (ILP) with a particular architecture. Unfortunately, these studies indicate...
Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masa...
MICRO
2010
IEEE
130views Hardware» more  MICRO 2010»
15 years 1 months ago
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
Minseon Ahn, Eun Jung Kim
AOSD
2009
ACM
15 years 10 months ago
The art of the meta-aspect protocol
ive semantics for aspect-oriented abstractions can be defined by language designers using extensible aspect compiler frameworks. However, application developers are prevented fro...
Tom Dinkelaker, Mira Mezini, Christoph Bockisch
DELTA
2010
IEEE
15 years 9 months ago
Algorithm Transformation for FPGA Implementation
— High level hardware description languages aim to make hardware design more like programming software. These languages are often used to accelerate legacy software algorithms by ...
Donald G. Bailey, Christopher T. Johnston