931 search results - page 128 / 187 » Compiling for vector-thread architectures |
159
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DAC
2007
ACM
16 years 3 months ago
2007
ACM
This paper argues for an implicitly parallel programming model for many-core microprocessors, and provides initial technical approaches towards this goal. In an implicitly paralle...
123
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DAC
2006
ACM
16 years 3 months ago
2006
ACM
In this paper, we present a methodology for low-cost and rapid context switch for multithreaded embedded processors with realtime guarantees. Context-switch, which involves saving...
112
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LCTRTS
2010
Springer
15 years 9 months ago
2010
Springer
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and movi...
132
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LCTRTS
2007
Springer
15 years 8 months ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
221
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ISLPED
2005
ACM
15 years 8 months ago
2005
ACM
In this paper, we take the idea of application-level processing on disks to one level further, and focus on an architecture, called Cluster of Active Disks (CAD), where the storag...