183 search results - page 4 / 37 » Complementing software pipelining with software thread integ... |
ASAP
2000
IEEE
14 years 1 months ago
2000
IEEE
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded proces...
CC
2000
Springer
13 years 9 months ago
2000
Springer
The performance of a Java Virtual Machine (JVM) interpreter running on a very long instruction word (VLIW) processor can be improved by means of pipelining. While one bytecode is i...
IPPS
1998
IEEE
14 years 2 months ago
1998
IEEE
In this paper, we propose an integrated approach for register-sensitive software pipelining. In this approach, the heuristics proposed in the stage scheduling method of Eichenberg...
FPL
2007
Springer
14 years 4 months ago
2007
Springer
Modern platform FPGAs integrate fine-grained reconfigurable logic with processor cores and allow the creation of complete configurable systems-on-chip. However, design methodol...
DAC
1996
ACM
14 years 1 months ago
1996
ACM
Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...