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FPGA
2008
ACM
142views FPGA» more  FPGA 2008»
15 years 4 months ago
Modeling routing demand for early-stage FPGA architecture development
Architecture development for FPGAs has typically been a very empirical discipline, requiring the synthesis of benchmark circuits into candidate architectures. This is difficult to...
Wei Mark Fang, Jonathan Rose
112
Voted
DAGSTUHL
2004
15 years 4 months ago
SHIM: A Language for Hardware/Software Integration
Virtually every system designed today is an amalgam of hardware and software. Unfortunately, software and circuits that communicate across the hardware/software boundary are tedio...
Stephen A. Edwards
122
Voted
ICCAD
2010
IEEE
140views Hardware» more  ICCAD 2010»
15 years 17 days ago
Reduction of interpolants for logic synthesis
Craig Interpolation is a state-of-the-art technique for logic synthesis and verification, based on Boolean Satisfiability (SAT). Leveraging the efficacy of SAT algorithms, Craig In...
John D. Backes, Marc D. Riedel
151
Voted
ASE
2005
140views more  ASE 2005»
15 years 2 months ago
Automated Procedure Construction for Deductive Synthesis
Deductive program synthesis systems based on automated theorem proving offer the promise of software that is correct by construction. However, the difficulty encountered in constru...
Steve Roach, Jeffrey Van Baalen
DATE
2007
IEEE
109views Hardware» more  DATE 2007»
15 years 9 months ago
Area optimization of multi-cycle operators in high-level synthesis
Conventional high-level synthesis algorithms usually employ multi-cycle operators to reduce the cycle length in order to improve the circuit performance. These operators need seve...
María C. Molina, Rafael Ruiz-Sautua, Jose M...