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JUCS
2000
120views more  JUCS 2000»
13 years 7 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
LOGCOM
2000
63views more  LOGCOM 2000»
13 years 7 months ago
Reflection principles in computational logic
We introduce the concept of reflection principle as a knowledge representation paradigm in a computational logic setting. Reflection principles are expressed as certain kinds of l...
Jonas Barklund, Pierangelo Dell'Acqua, Stefania Co...
CGA
1999
13 years 7 months ago
Vector Geometry for Computer Graphics
translating your abstract notions of desired size and shape directly into the appropriate tugs and pulls. You would probably not think much about coordinate systems. Ifyouwantedtom...
James R. Miller
NAR
2002
138views more  NAR 2002»
13 years 7 months ago
The KEGG databases at GenomeNet
The Kyoto Encyclopedia of Genes and Genomes (KEGG) is the primary database resource of the Japanese GenomeNet service (http://www.genome.ad.jp/) for understanding higher order fun...
Minoru Kanehisa, Susumu Goto, Shuichi Kawashima, A...
TC
1998
13 years 7 months ago
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
—The very high levels of integration and submicron device sizes used in current and emerging VLSI technologies for FPGAs lead to higher occurrences of defects and operational fau...
Fran Hanchek, Shantanu Dutt