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» Completeness Results for Memory Logics
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FTCS
1994
140views more  FTCS 1994»
13 years 10 months ago
Concurrent Error Detection in Self-Timed VLSI
This paper examines architectural techniques for providing concurrent error detection in self-timed VLSI pipelines. Signal pairs from Differential Cascode Voltage Switch Logic are...
David A. Rennels, Hyeongil Kim
CSL
2007
Springer
14 years 3 months ago
On the Complexity of Reasoning About Dynamic Policies
We study the complexity of satisfiability for DLP+ dyn , an expressive logic introduced by Demri that allows to reason about dynamic policies. DLP+ dyn extends the logic DLPdyn of...
Stefan Göller
LPNMR
2007
Springer
14 years 3 months ago
Alternative Characterizations for Program Equivalence under Answer-Set Semantics: Preliminary Report
Logic programs under answer-set semantics constitute an important tool for declarative problem solving. In recent years, two research issues received growing attention. On the one ...
Martin Gebser, Torsten Schaub, Hans Tompits, Stefa...
TARK
2007
Springer
14 years 2 months ago
What can we achieve by arbitrary announcements?: A dynamic take on Fitch's knowability
Public announcement logic is an extension of multi-agent epistemic logic with dynamic operators to model the informational consequences of announcements to the entire group of age...
Philippe Balbiani, Alexandru Baltag, Hans P. van D...
ISPD
1999
ACM
128views Hardware» more  ISPD 1999»
14 years 1 months ago
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and dom...
Michael A. Riepe, Karem A. Sakallah