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» Completeness Results for Memory Logics
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ISSS
2002
IEEE
142views Hardware» more  ISSS 2002»
14 years 1 months ago
Energy/Power Estimation of Regular Processor Arrays
We propose a high-level analytical model for estimating the energy and/or power dissipation in VLSI processor (systolic) array implementations of loop programs, particularly for i...
Sanjay V. Rajopadhye, Steven Derrien
CODES
2007
IEEE
14 years 3 months ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling
CASES
2005
ACM
13 years 10 months ago
Segment protection for embedded systems using run-time checks
The lack of virtual memory protection is a serious source of unreliability in many embedded systems. Without the segment-level protection it provides, these systems are subject to...
Matthew Simpson, Bhuvan Middha, Rajeev Barua
JANCL
2007
74views more  JANCL 2007»
13 years 8 months ago
Operations on proofs and labels
Logic of proofs LP introduced by S. Artemov in 1995 describes properties of proof predicate “t is a proof of F” in the propositional language extended by atoms of the form [[t...
Tatiana Yavorskaya, Natalia Rubtsova
KDD
1999
ACM
199views Data Mining» more  KDD 1999»
14 years 1 months ago
The Application of AdaBoost for Distributed, Scalable and On-Line Learning
We propose to use AdaBoost to efficiently learn classifiers over very large and possibly distributed data sets that cannot fit into main memory, as well as on-line learning wher...
Wei Fan, Salvatore J. Stolfo, Junxin Zhang