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ICCAD
2009
IEEE
106views Hardware» more  ICCAD 2009»
13 years 6 months ago
An efficient pre-assignment routing algorithm for flip-chip designs
The flip-chip package is introduced for modern IC designs with higher integration density and larger I/O counts. In this paper, we consider the pre-assignment flip-chip routing pr...
Po-Wei Lee, Chung-Wei Lin, Yao-Wen Chang, Chin-Fan...
WSC
2008
13 years 11 months ago
Discrete Rate Simulation using linear programming
Discrete Rate Simulation (DRS) is a modeling methodology that uses event based logic to simulate linear continuous processes and hybrid systems. These systems are concerned with t...
Cecile Damiron, Anthony Nastasi
CORR
2008
Springer
106views Education» more  CORR 2008»
13 years 8 months ago
Distributed Algorithms for Computing Alternate Paths Avoiding Failed Nodes and Links
A recent study characterizing failures in computer networks shows that transient single element (node/link) failures are the dominant failures in large communication networks like...
Amit M. Bhosle, Teofilo F. Gonzalez
ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
14 years 22 days ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
ISCA
2005
IEEE
101views Hardware» more  ISCA 2005»
14 years 2 months ago
Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks
Minimizing latency and maximizing throughput are important goals in the design of routing algorithms for interconnection networks. Ideally, we would like a routing algorithm to (a...
Daeho Seo, Akif Ali, Won-Taek Lim, Nauman Rafique,...