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» Complexity Analysis of H.264 Decoder for FPGA Design
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ICCD
2008
IEEE
202views Hardware» more  ICCD 2008»
14 years 4 months ago
CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework
— Extreme scaling practices in silicon technology are quickly leading to integrated circuit components with limited reliability, where phenomena such as early-transistor failures...
Andrea Pellegrini, Kypros Constantinides, Dan Zhan...
ICC
2007
IEEE
245views Communications» more  ICC 2007»
14 years 1 months ago
Low Complexity MMSE Vector Precoding Using Lattice Reduction for MIMO Systems
—In this paper, a lattice-reduction-aided (LRA) With such an approximation, the complexity of VP is greatly minimum mean square error (MMSE) vector precoding (VP) is reduced. pro...
Feng Liu, Ling-ge Jiang, Chen He
DSD
2010
IEEE
161views Hardware» more  DSD 2010»
13 years 7 months ago
Design of Trace-Based Split Array Caches for Embedded Applications
—Since many embedded systems execute a predefined set of programs, tuning system components to application programs and data is the approach chosen by many design techniques to o...
Alice M. Tokarnia, Marina Tachibana
ISQED
2010
IEEE
156views Hardware» more  ISQED 2010»
13 years 9 months ago
On the design of different concurrent EDC schemes for S-Box and GF(p)
Recent studies have shown that an attacker can retrieve confidential information from cryptographic hardware (e.g. the secret key) by introducing internal faults. A secure and re...
Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir,...
DAC
2005
ACM
14 years 8 months ago
Hardware speech recognition for user interfaces in low cost, low power devices
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer