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ISPD
2010
ACM
207views Hardware» more  ISPD 2010»
14 years 2 months ago
FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction
Obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) construction is becoming one of the most sought after problems in modern design flow. In this paper we present FOARS, ...
Gaurav Ajwani, Chris Chu, Wai-Kei Mak
ISQED
2009
IEEE
94views Hardware» more  ISQED 2009»
14 years 2 months ago
Simultaneous buffer and interlayer via planning for 3D floorplanning
As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...
Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong
VMCAI
2009
Springer
14 years 2 months ago
SubPolyhedra: A (More) Scalable Approach to Infer Linear Inequalities
Abstract. We introduce Subpolyhedra (SubPoly) a new numerical abstract domain to infer and propagate linear inequalities. SubPoly is as expressive as Polyhedra, but it drops some o...
Vincent Laviron, Francesco Logozzo
ISLPED
2006
ACM
122views Hardware» more  ISLPED 2006»
14 years 1 months ago
Dynamic thermal clock skew compensation using tunable delay buffers
—The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular, by increasing the skew of the clock net and/or alteri...
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Vi...
ASPDAC
2005
ACM
73views Hardware» more  ASPDAC 2005»
14 years 1 months ago
An-OARSMan: obstacle-avoiding routing tree construction with good length performance
- Routing is one of the important steps in VLSI/ULSI physical design. The rectilinear Steiner minimum tree (RSMT) construction is an essential part of routing. Since macro cells, I...
Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng 0002, Xi...