Obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) construction is becoming one of the most sought after problems in modern design flow. In this paper we present FOARS, ...
As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...
Abstract. We introduce Subpolyhedra (SubPoly) a new numerical abstract domain to infer and propagate linear inequalities. SubPoly is as expressive as Polyhedra, but it drops some o...
—The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular, by increasing the skew of the clock net and/or alteri...
- Routing is one of the important steps in VLSI/ULSI physical design. The rectilinear Steiner minimum tree (RSMT) construction is an essential part of routing. Since macro cells, I...