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» Complexity-Effective Superscalar Processors
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ISLPED
1998
ACM
86views Hardware» more  ISLPED 1998»
13 years 11 months ago
The energy complexity of register files
Register files (RF) represent a substantial portion of the energy budget in modern processors, and are growing rapidly with the trend towards wider instruction issue. The actual ...
Victor V. Zyuban, Peter M. Kogge
MICRO
1996
IEEE
129views Hardware» more  MICRO 1996»
13 years 11 months ago
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
Eric Rotenberg, Steve Bennett, James E. Smith
MICRO
1992
IEEE
128views Hardware» more  MICRO 1992»
13 years 11 months ago
MISC: a Multiple Instruction Stream Computer
This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC arch...
Gary S. Tyson, Matthew K. Farrens, Andrew R. Plesz...
ARCS
2006
Springer
13 years 11 months ago
Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?
While trace cache, value prediction, and prefetching have been shown to be effective in the single-threaded superscalar, there has been no analysis of these techniques in a Simulta...
Chen-Yong Cher, Il Park, T. N. Vijaykumar
PACS
2000
Springer
110views Hardware» more  PACS 2000»
13 years 11 months ago
Compiler-Directed Dynamic Frequency and Voltage Scheduling
Dynamic voltage and frequency scaling has been identified as one of the most effective ways to reduce power dissipation. This paper discusses a compilation strategy that identifies...
Chung-Hsing Hsu, Ulrich Kremer, Michael S. Hsiao