Deeply pipelined, superscalar processors require accurate branch prediction to achieve high performance. Two-level branch predictors have been shown to achieve high prediction acc...
Eric Sprangle, Robert S. Chappell, Mitch Alsup, Ya...
Exploitation ofinstruction-levelparallelism is an ejfective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be appl...
Power consumption has become a very important metric and challenging research topic in the design of microprocessors in the recent years. The goal of this work is to improve power...
Frederico Pratas, Georgi Gaydadjiev, Mladen Bereko...
We explore different prefetch distance-degree combinations and very simple, low-cost adaptive policies on a superscalar core with a high bandwidth, high capacity on-chip memory hie...
- With the intention of reduce significantly the energy that wastes away when having a read or write access to the register file, since the technique Zero Detect diminishes the tra...
Moises Zarate, Oscar Camacho Nieto, Luis A. Villa ...