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ISCA
1997
IEEE
119views Hardware» more  ISCA 1997»
13 years 11 months ago
The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference
Deeply pipelined, superscalar processors require accurate branch prediction to achieve high performance. Two-level branch predictors have been shown to achieve high prediction acc...
Eric Sprangle, Robert S. Chappell, Mitch Alsup, Ya...
MICRO
1995
IEEE
217views Hardware» more  MICRO 1995»
13 years 11 months ago
Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation
Exploitation ofinstruction-levelparallelism is an ejfective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be appl...
Jack W. Davidson, Sanjay Jinturkar
CF
2008
ACM
13 years 9 months ago
Low power microarchitecture with instruction reuse
Power consumption has become a very important metric and challenging research topic in the design of microprocessors in the recent years. The goal of this work is to improve power...
Frederico Pratas, Georgi Gaydadjiev, Mladen Bereko...
EUROPAR
2008
Springer
13 years 9 months ago
Low-Cost Adaptive Data Prefetching
We explore different prefetch distance-degree combinations and very simple, low-cost adaptive policies on a superscalar core with a high bandwidth, high capacity on-chip memory hie...
Luis M. Ramos, José Luis Briz, Pablo E. Ib&...
CDES
2006
74views Hardware» more  CDES 2006»
13 years 9 months ago
Zero Detect-Based Low Power Registers File Access
- With the intention of reduce significantly the energy that wastes away when having a read or write access to the register file, since the technique Zero Detect diminishes the tra...
Moises Zarate, Oscar Camacho Nieto, Luis A. Villa ...