Sciweavers

271 search results - page 42 / 55
» Complexity-Effective Superscalar Processors
Sort
View
SBACPAD
2004
IEEE
97views Hardware» more  SBACPAD 2004»
13 years 9 months ago
IATO: A Flexible EPIC Simulation Environment
High-performance superscalar processors are designed with the help of complex simulation environment. The simulation infrastructure permits to validate the processor instruction s...
Amaury Darsch, André Seznec
ASAP
2003
IEEE
124views Hardware» more  ASAP 2003»
14 years 25 days ago
Arbitrary Bit Permutations in One or Two Cycles
Symmetric-key block ciphers encrypt data, providing data confidentiality over the public Internet. For inter-operability reasons, it is desirable to support a variety of symmetric...
Zhijie Shi, Xiao Yang, Ruby B. Lee
CGO
2003
IEEE
14 years 25 days ago
Dynamic Binary Translation for Accumulator-Oriented Architectures
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
Ho-Seop Kim, James E. Smith
MICRO
2002
IEEE
97views Hardware» more  MICRO 2002»
14 years 13 days ago
Three extensions to register integration
Register integration (or just integration) is a register renaming discipline that implements instruction reuse via physical register sharing. Initially developed to perform squash...
Vlad Petric, Anne Bracy, Amir Roth
ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
13 years 12 months ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...