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DATE
2006
IEEE
84views Hardware» more  DATE 2006»
14 years 2 months ago
Vulnerability analysis of L2 cache elements to single event upsets
Memory elements are the most vulnerable system component to soft errors. Since memory elements in cache arrays consume a large fraction of the die in modern microprocessors, the p...
Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Ta...
MEMOCODE
2006
IEEE
14 years 2 months ago
Latency-insensitive design and central repetitive scheduling
The theory of latency-insensitive design (LID) was recently invented to cope with the time closure problem in otherwise synchronous circuits and programs. The idea is to allow the...
Julien Boucaron, Robert de Simone, Jean-Vivien Mil...
RTSS
2006
IEEE
14 years 2 months ago
Run-Time Services for Hybrid CPU/FPGA Systems on Chip
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
Jason Agron, Wesley Peck, Erik Anderson, David L. ...
ACISP
2006
Springer
14 years 2 months ago
Towards Provable Security for Ubiquitous Applications
Abstract. The emergence of computing environments where smart devices are embedded pervasively in the physical world has made possible many interesting applications and has trigger...
Mike Burmester, Tri Van Le, Breno de Medeiros
ASPLOS
2006
ACM
14 years 2 months ago
ExecRecorder: VM-based full-system replay for attack analysis and system recovery
Log-based recovery and replay systems are important for system reliability, debugging and postmortem analysis/recovery of malware attacks. These systems must incur low space and p...
Daniela A. S. de Oliveira, Jedidiah R. Crandall, G...