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ISCA
2000
IEEE
99views Hardware» more  ISCA 2000»
15 years 9 months ago
Transient fault detection via simultaneous multithreading
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
Steven K. Reinhardt, Shubhendu S. Mukherjee
CRYPTO
2000
Springer
133views Cryptology» more  CRYPTO 2000»
15 years 9 months ago
Sequential Traitor Tracing
Traceability schemes allow detection of at least one traitor when a group of colluders attempt to construct a pirate decoder and gain illegal access to digital content. Fiat and Ta...
Reihaneh Safavi-Naini, Yejing Wang
PLDI
1999
ACM
15 years 9 months ago
Load-Reuse Analysis: Design and Evaluation
Load-reuse analysis finds instructions that repeatedly access the same memory location. This location can be promoted to a register, eliminating redundant loads by reusing the re...
Rastislav Bodík, Rajiv Gupta, Mary Lou Soff...
134
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MICRO
1999
IEEE
105views Hardware» more  MICRO 1999»
15 years 9 months ago
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
Todd M. Austin
ISCA
1998
IEEE
151views Hardware» more  ISCA 1998»
15 years 9 months ago
Alternative Implementations of Two-Level Adaptive Branch Prediction
As the issue rate and depth of pipelining of high performance Superscalar processors increase, the importance of an excellent branch predictor becomes more vital to delivering the...
Tse-Yu Yeh, Yale N. Patt
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