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» Computational Intelligence in Circuit Synthesis
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DAC
1996
ACM
14 years 26 days ago
Power Estimation of Cell-Based CMOS Circuits
PPP is a Web-based simulation and synthesis environment for low-power design. In this paper we describe the gate-level simulation engine of PPP, that achieves accuracy always with...
Alessandro Bogliolo, Luca Benini, Bruno Ricc&ograv...
DAC
1995
ACM
14 years 8 days ago
Automatic Layout Synthesis of Leaf Cells
––This paper describes algorithms for automatic layout synthesisofleafcellsin1–dandinanew1–1/2–dlayoutstyle,useful for non–dual circuit styles. The graph theory based a...
Sanjay Rekhi, J. Donald Trotter, Daniel H. Linder
CEC
2007
IEEE
13 years 10 months ago
Fitness inheritance in evolutionary and multi-objective high-level synthesis
Abstract—The high-level synthesis process allows the automatic design and implementation of digital circuits starting from a behavioral description. Evolutionary algorithms are v...
Christian Pilato, Gianluca Palermo, Antonino Tumeo...
ISQED
2009
IEEE
112views Hardware» more  ISQED 2009»
14 years 3 months ago
Estimation and optimization of reliability of noisy digital circuits
— With continued scaling, reliability is emerging as a critical challenge for the designers of digital circuits. The challenge stems in part from the lack of computationally efï¬...
Satish Sivaswamy, Kia Bazargan, Marc D. Riedel
ISMVL
2010
IEEE
209views Hardware» more  ISMVL 2010»
14 years 1 months ago
Secure Design Flow for Asynchronous Multi-valued Logic Circuits
—The purpose of secure devices such as smartcards is to protect secret information against software and hardware attacks. Implementation of the appropriate protection techniques ...
Ashur Rafiev, Julian P. Murphy, Alexandre Yakovlev