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» Computational Intelligence in Circuit Synthesis
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DAC
1994
ACM
14 years 25 days ago
Statistical Delay Modeling in Logic Design and Synthesis
Manufacturing disturbances are inevitable in the fabrication of integrated circuits. These disturbances will result in variations in the delay speci cations of manufactured circui...
Horng-Fei Jyu, Sharad Malik
DAC
1995
ACM
14 years 9 days ago
A Survey of Optimization Techniques Targeting Low Power VLSI Circuits
—We survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are cons...
Srinivas Devadas, Sharad Malik
APN
2005
Springer
14 years 2 months ago
Determinate STG Decomposition of Marked Graphs
STGs give a formalism for the description of asynchronous circuits based on Petri nets. To overcome the state explosion problem one may encounter during circuit synthesis, a nondet...
Mark Schäfer, Walter Vogler, Petr Jancar
ISMVL
2010
IEEE
195views Hardware» more  ISMVL 2010»
14 years 1 months ago
ESOP-Based Toffoli Network Generation with Transformations
In this paper a new Toffoli gate cascade synthesis method is presented. This method is based on previous work [12] and generates a cascade of inverted-control-Toffoli gates from t...
Yasaman Sanaee, Gerhard W. Dueck