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FPL
2009
Springer
154views Hardware» more  FPL 2009»
14 years 1 days ago
Compiler assisted runtime task scheduling on a reconfigurable computer
Multitasking reconfigurable computers with one or more reconfigurable processors are being used increasingly during the past few years. One of the major challenges in such systems...
Mojtaba Sabeghi, Vlad Mihai Sima, Koen Bertels
NOCS
2010
IEEE
13 years 5 months ago
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
Abstract--The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face...
Samuel Rodrigo, Jose Flich, Antoni Roca, Simone Me...
DATE
2009
IEEE
146views Hardware» more  DATE 2009»
14 years 2 months ago
System-level power/performance evaluation of 3D stacked DRAMs for mobile applications
Abstract—Convergence of communication, consumer applications and computing within mobile systems pushes memory requirements both in terms of size, bandwidth and power consumption...
Marco Facchini, Trevor Carlson, Anselme Vignon, Ma...
GIR
2007
ACM
13 years 11 months ago
Visualising the south Yorkshire floods of '07
This paper describes initial work on developing an information system to gather, process and visualise various multimedia data sources related to the South Yorkshire (UK) floods o...
Paul Clough, Robert Pasley, Stefan Siersdorfer, Jo...
MICRO
2009
IEEE
207views Hardware» more  MICRO 2009»
14 years 2 months ago
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
Gabriel H. Loh