Sciweavers

1019 search results - page 187 / 204
» Computer Aided Ferret Design
Sort
View
DAC
2009
ACM
14 years 7 months ago
Online cache state dumping for processor debug
Post-silicon processor debugging is frequently carried out in a loop consisting of several iterations of the following two key steps: (i) processor execution for some duration, fo...
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishna...
DAC
2009
ACM
14 years 7 months ago
Process variation characterization of chip-level multiprocessors
Within-die variation in leakage power consumption is substantial and increasing for chip-level multiprocessors (CMPs) and multiprocessor systems-on-chip. Dealing with this problem...
Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, ...
DAC
2008
ACM
14 years 7 months ago
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
In this paper, we present ELIAD, an efficient lithography aware detailed router to optimize silicon image after optical proximity correction (OPC) in a correct-by-construction man...
Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan
DAC
2008
ACM
14 years 7 months ago
DeFer: deferred decision making enabled fixed-outline floorplanner
In this paper, we present DeFer -- a fast, high-quality and nonstochastic fixed-outline floorplanning algorithm. DeFer generates a non-slicing floorplan by compacting a slicing fl...
Jackey Z. Yan, Chris Chu
DAC
2002
ACM
14 years 7 months ago
ILP-based engineering change
We have developed a generic integer linear programming(ILP)based engineering change(EC) methodology. The EC methodology has three components: enabling, fast, and preserving. Enabl...
Farinaz Koushanfar, Jennifer L. Wong, Jessica Feng...