671 search results - page 53 / 135 » Computer Aided Modelling Exercises |
DAC
2006
ACM
14 years 3 months ago
2006
ACM
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing an...
CSIE
2009
IEEE
14 years 4 months ago
2009
IEEE
Building a model using machine learning that can classify the sentiment of natural language text often requires an extensive set of labeled training data from the same domain as t...
VLSID
2002
IEEE
14 years 10 months ago
2002
IEEE
Predictive delay analysis is presented for a representative CMOS inverter with submicron device size using PREDICTMOS MOSFET model. As against SPICE, which adopts a time consuming...
DAC
2005
ACM
13 years 12 months ago
2005
ACM
We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model...