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CAD
2006
Springer
13 years 7 months ago
Parametric interpolation using sampled data
, and of course, you have the option to download any article straight to your desktop, depending on your access rights. Read more about how the TOP 25 is generated and what it refl...
Soon Yong Jeong, Yun Jong Choi, PooGyeon Park
ISQED
2005
IEEE
98views Hardware» more  ISQED 2005»
14 years 1 months ago
Wire Planning with Bounded Over-the-Block Wires
Hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the lowlevel designs have to have a global view of h...
Hua Xiang, I-Min Liu, Martin D. F. Wong
DAC
2006
ACM
14 years 1 months ago
Variation-aware analysis: savior of the nanometer era?
VLSI engineers have traditionally used a variety of CAD analysis tools (e.g. SPICE) to deal with variability. As we go into deep sub micron issues, the analysis is becoming harder...
Sani R. Nassif, Vijay Pitchumani, N. Rodriguez, De...
CODES
2005
IEEE
14 years 1 months ago
Key research problems in NoC design: a holistic perspective
Networks-on-Chip (NoCs) have been recently proposed as a promising solution to complex on-chip communication problems. The lack of an unified representation of applications and ar...
Ümit Y. Ogras, Jingcao Hu, Radu Marculescu
GECCO
2005
Springer
127views Optimization» more  GECCO 2005»
14 years 1 months ago
Evolutionary form-finding of tensegrity structures
Tensegrity structures are stable 3-dimensional mechanical structures which maintain their form due to an intricate balance of forces between disjoint rigid elements and continuous...
Chandana Paul, Hod Lipson, Francisco J. Valero Cue...