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» Computing an Optimal Layout for Cone Trees
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ARITH
2003
IEEE
14 years 21 days ago
High-Performance Left-to-Right Array Multiplier Design
We propose a split array multiplier organized in a left-to-right leapfrog (LRLF) structure with reduced delay compared to conventional array multipliers. Moreover, the proposed de...
Zhijun Huang, Milos D. Ercegovac
EURODAC
1994
IEEE
127views VHDL» more  EURODAC 1994»
13 years 11 months ago
Optimal equivalent circuits for interconnect delay calculations using moments
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
Sudhakar Muddu, Andrew B. Kahng
MOBIHOC
2012
ACM
11 years 10 months ago
Oblivious low-congestion multicast routing in wireless networks
We propose a routing scheme to implement multicast communication in wireless networks. The scheme is oblivious, compact, and completely decentralized. It is intended to support dy...
Antonio Carzaniga, Koorosh Khazaei, Fabian Kuhn
DAC
2008
ACM
14 years 8 months ago
DeFer: deferred decision making enabled fixed-outline floorplanner
In this paper, we present DeFer -- a fast, high-quality and nonstochastic fixed-outline floorplanning algorithm. DeFer generates a non-slicing floorplan by compacting a slicing fl...
Jackey Z. Yan, Chris Chu
FPGA
1999
ACM
142views FPGA» more  FPGA 1999»
13 years 11 months ago
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems
Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we addr...
Abdel Ejnioui, N. Ranganathan