In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
Aniruddha N. Udipi, Naveen Muralimanohar, Niladris...
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...
The best known upper bound on the number of topological changes in the Delaunay triangulation of a set of moving points in R2 is (nearly) cubic, even if each point is moving with ...
Pankaj K. Agarwal, Jie Gao, Leonidas J. Guibas, Ha...
The rapid advancement in wireless communication technology has spurred significant interest in the design and development of enhanced TCP protocols. Among them, TCP Westwood (TCPW...
Ren Wang, Massimo Valla, M. Y. Sanadidi, Mario Ger...