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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 23 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ISCA
2010
IEEE
305views Hardware» more  ISCA 2010»
14 years 23 days ago
Rethinking DRAM design and organization for energy-constrained multi-cores
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
Aniruddha N. Udipi, Naveen Muralimanohar, Niladris...
CF
2010
ACM
14 years 23 days ago
Interval-based models for run-time DVFS orchestration in superscalar processors
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...
Georgios Keramidas, Vasileios Spiliopoulos, Stefan...
COMPGEOM
2010
ACM
14 years 23 days ago
Kinetic stable Delaunay graphs
The best known upper bound on the number of topological changes in the Delaunay triangulation of a set of moving points in R2 is (nearly) cubic, even if each point is moving with ...
Pankaj K. Agarwal, Jie Gao, Leonidas J. Guibas, Ha...
ICNP
2002
IEEE
14 years 19 days ago
Using Adaptive Rate Estimation to Provide Enhanced and Robust Transport over Heterogeneous Networks
The rapid advancement in wireless communication technology has spurred significant interest in the design and development of enhanced TCP protocols. Among them, TCP Westwood (TCPW...
Ren Wang, Massimo Valla, M. Y. Sanadidi, Mario Ger...
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