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» Computing in the Presence of Timing Failures
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CORR
2011
Springer
143views Education» more  CORR 2011»
12 years 11 months ago
Non-malleable extractors via character sums
In studying how to communicate over a public channel with an active adversary, Dodis and Wichs introduced the notion of a non-malleable extractor. A non-malleable extractor dramat...
Trevor D. Wooley, David Zuckerman
DAC
2005
ACM
14 years 8 months ago
Robust gate sizing by geometric programming
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, ...
LCTRTS
2007
Springer
14 years 1 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
PR
2008
228views more  PR 2008»
13 years 7 months ago
Accurate integration of multi-view range images using k-means clustering
3D modelling finds a wide range of applications in industry. However, due to the presence of surface scanning noise, accumulative registration errors, and improper data fusion, re...
Hong Zhou, Yonghuai Liu
VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
14 years 8 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty